The present invention relates generally to digital signal processing, and more specifically to filtering circuits used to filter digital data.
Generally, programmable logic devices (PLD) such as field programmable gate arrays (FPGA), include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables (LUTs) to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as serializers, deserializers, filters, adders, multiply and accumulate circuits, and phase-locked loops (PLL). The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
Due to their programmability and flexible circuit functionality, PLDs are increasingly being used for digital signal processing (DSP) functions. DSP functions are employed to process digital signals used in personal entertainment system, wireless communication, remote medical diagnosis, etc. For example, FPGAs are often configured and employed to process digital signals used in modern cellular phone systems, studio editing equipment, high definition televisions, etc.
Digital data may be derived from many sources and transmitted in a serial or parallel fashion depending on the transmission methodology. For example, digital data may be derived from analog data such as a voice or music and transmitted as a serial or parallel digital signal to a digital receiver. Illustratively, an analog-to-digital converter (A/D) converter may be used in a cellular phone to convert a voice of one caller to a parallel digital signal. The parallel digital signal is processed by a DSP processing device, such as an FPGA, embedded in the caller's cellular phone to produce a digital signal suitable for transmission over the cellular network. The digital signal is transmitted by the caller's cellular phone to another cellular phone in the cellular network using cellular network transmission data transmission protocols and methods. A DSP device in the other cellular phone receives the digital signal, processes the digital signal, and outputs a digital signal to a digital-to-analog (D/A) converter to convert the digital data back to analog speech.
Unfortunately, conventional DSP device data processing throughput is constrained by its maximum operating clock rate (e.g., maximum operating clock frequency). For example, conventional digital systems employing DSP filters, such as conventional DSP filters, are limited to filtering digital signals at a processing speed which cannot extend beyond the operating clock rate of the DSP filter, thereby limiting the overall throughput of the digital system. While increasing the processing speed of the DSP filter is a one solution typically sought by the DSP device industry, increasing the operating clock rate of the DSP device is often constrained by operational frequency limitations of internal devices and/or device development costs.
Accordingly, it is desirable to have circuits, methods, and an apparatus for implementing an improved DSP filter that allows for increased DSP processing throughput without requiring the increase of the DSP operating clock rate or device development cost.